Introduction of electronics to young kids [Blast from the past]

I was introduced to electronics at a very young age. This was partially because my father was an electrical engineer, although he was spent most of his time outside hometown. But, I think the main reason was I always had this urge to understand things. And electronics really seemed to be abstract, and so I spent significant amount of time figure out the connections in any electronics device which I was allowed to take apart. I even broke a remote control toy (the ones that get boring really fast) to take out the motor and to use it to build a hovercraft.

Anyway fast forward, I entered Jadavpur University to do my majors in Instrumentation and Electronics Engineering. I took up pursuing electronics both as a hobbyist, and to build a career in electronics. But what I found was that people did not appreciate electronics. The way electronics is taught in most places in India is completely crap.

During the third year of my studies, some students came up with the idea of a TechknowCradle, a program in which we can conduct workshops on basic sciences. We decided to make the workshop such that it is a deviation from the rote learning routines most students of developing countries follow. But then I proposed that I will teach electronics. I also wanted to have a hands on session where I would ask the students to solder some components, give them some resistors and ask them o determine their values using multimeters etc.

But then I wanted to teach them something that would be altogether different. So, I picked relays. Electro-mechanical relays are derived from a simple concept, but has immense use.

For their final project, I taught them how to make a wired remote control car using double pole double throw switches.

The session was spread over two days. On the first day, the theoretical session was after lunch and went on till the evening. The following day we started with the hands on early in the morning.

At the end of it all, there was an award ceremony planned for the students. One of the students said, and I think its the best compliment I have ever received, 'I hated electronics before this, now thanks to Vivek da [a sort of informal salutation that stands for elder brother], I want to be an electronics engineer.'

And this was my experience from 2013. Its been more than 4 years. But at every phase, I have always and always wanted to teach young children the magic of electronics and hardware in general. As Peter Thiel once said, 'We wanted flying cars but what we got was 140 characters'. If we want science fiction to come true [things like flying cars, cheaper space explorations, more automation], we need to keep teaching young kids how to build the skeletons. I am by no means trying to downplay the importance of software development or the difficulties associated in it, but somehow the interest in hardware is on the decline. I don't want that to happen.

I managed to dig out a copy of the presentation: TechknowCradle_ppt

Verilog code for checksum

I have never used Verilog (well I am used to VerilogA), and back during my undergraduate days HDL was VHDL for me. The industry at large seems to prefer Verilog, and I decided to catch up on the basics before I head out to Leuven.
Looking for problem, I came across a slide from NCSU. The problem was:

//There are 9 bytes of data.
//The first byte is the packet identifier. 2'h55 indicates a valid data packet containing 7 data bytes and // one checksum byte is following.
//The next seven bytes are data bytes.
//The last byte is the checksum
//If the sum of the 7 data bytes truncated to 8 bits do not match the checksum byte,
//the error signal is to be asserted and kept high until the next valid data byte starts appearing

This was the code I wrote:

`timescale 1ns / 1ps
//There are 9 bytes of data.
//The first byte is the packet identifier. 2'h55 indicates a valid data packet is follwoing
//The next seven bytes are data bytes.
//The last byte is the checksum
//If the sum of the 7 data bytes truncated to 8 bits do not match the checksum byte,
//the error signal is to be asserted and kept high until the next valid data byte starts appearing
module check_sum(
    input clk,
    input reset_bar,
    input [7:0] data,
    output error
    );
    reg [7:0]internal_sum;
    reg [2:0]state_vec;
    reg [3:0]byte_count;
    reg error_state;
    always @(posedge clk or negedge reset_bar) begin
        if (~reset_bar) begin
            state_vec=3'b000;
            error_state=1'b0;
            internal_sum=0;
            byte_count=0;
        end
        else if (state_vec == 3'b000) begin
                //this means it is waiting for new data frame
                //check whether the data is 2'h55 or not.
                internal_sum=0; //since we are wiating for a new data frame, sum is set to zero
                if (data==8'b01010101)begin
                    state_vec=3'b001; //1 indicates that it is ready to receive the data
                    error_state=0;
                end
                else begin
                    state_vec=3'b100; //4 indicates that it is in invalid data frame and should be ignored
                end
                byte_count=0;
            end
        else if (state_vec==3'b001) begin
                //increment byte counter
                byte_count=byte_count+1;
                internal_sum=internal_sum+data;
                if (byte_count==4'b0111) begin
                    //all seven bytes have been received. the next byte will be the checksum
                    state_vec=3'b010; //a value of 2 for the state vector indicates that it is ready for checksum cehck.
                end
         end
         else if (state_vec==3'b010) begin
                //reset the byte count
                byte_count=4'b0000;
                if (internal_sum != data)
                    error_state=1'b1;
                else
                    error_state=1'b0;
                state_vec=3'b000;
         end
         else if (state_vec==3'b100) begin
                //nothing to do really other than increment the byte counter
                byte_count=byte_count+1;
                if (byte_count==4'b1000) 
                    //received all the 7 bytes of data plus one checksum byte
                    state_vec=3'b000;
                else
                    state_vec=3'b100;
         end
     end
    assign error=error_state?1'b1:1'b0;
     
endmodule

The test bench that I used was:

`timescale 1ns / 1ps
module test_check_sum;
    reg [7:0]data;
    reg reset_bar;
    reg clk;
    wire error;
    integer i;
    integer k;
    reg [7:0]data_sum;
    check_sum DUT (clk,reset_bar,data,error);
    initial begin
        reset_bar=1'b1;
        data_sum=0;
        #10
        reset_bar=1'b0;
        #10
        reset_bar=1'b1;
        #5
        //we will run the simulation for 5 different data packets.
        for(i=0;i<5;i=i+1) begin
            data_sum=0;
            //data=8'h55; //to indicate the start of the packet
            if (i==1)
                data=8'h56;
            else
                data=8'h55;
            #40
            for(k=1;k<=7;k=k+1) begin
                data=$urandom_range(0,255);
                data_sum=data_sum+data;
                #40;
            end
            data=data_sum+1;
            #40;
        end
    end
    always begin
        clk=1'b0;
        #45
        clk=1'b1;
        forever begin
            #20
            clk=~clk;
        end
    end    
 endmodule

Here is a snap of the waveform:

Visit to Jadavpur University Science Club

I have been sitting idle in Kolkata for the last three weeks or so. (Well not completely).

I resigned from Cadence and left Bangalore on August 6th. I was scheduled to fly to Brussels around mid-September, and I decided to take some time off and spend time lazing around (something which I never got to do in the last three years). I also had to apply for visa etc.

Anyway, I was pinged on Facebook by a junior, Diyanko from my alum asking me to come down to Science Club (something which I was a part of during my college days, and also played a major role in getting it started). Now, I really did not want to come down there, and just chat and go.

I decided to give them a presentation on analog circuit design, and talk to them about some of the fundamentals that an analog design engineer requires every day. Given that students from first year to fourth year would be coming, and that students from non-electrical background will also be present, it was a challenge coming up with a presentation that could cover so many aspects.

It really took me some time to make the presentation, far more than I had imagined. I just could not talk about circuits, as that would have made it extremely boring for the younger folks in the audience as well as people from a non-electrical background. I had to pepper my presentation with examples from real life.

But cutting back to the chase, the presentation went really well. The best part that I like about students in Jadavpur University is that students are extremely talented, and they have this drive within themselves that want to do something. I met one final year student of ETCE, Supratik, who was interested in quantum computing and was looking for opportunities in Europe to do a MS on the same. This is refreshingly different. But what really pained me was that the analog courses in Jadavpur University had absolutely no emphasis on simulating the circuits and seeing it for themselves. A simulator gives you an excellent idea about whether your concepts are correct or not. And using one, can really help understand the concepts. You get an insight to the second and third order effects that one hasn’t considered.

Although I could not cover all the material I had put in my presentation due to a shortage of time, I think I did a cover a fair amount of material. 

Link to the presentation